Corrections to “Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs”

Zou J.; Xu Q.; Luo J.; Wang R.; Huang R.; Wang Y.

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Corrections to “Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs”

机译：对“全方位栅圆柱形硅纳米线MOSFET中的寄生栅电容的预测3-D建模”的更正

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来源
《Electron Devices, IEEE Transactions on》 |2012年第3期|p.867|共1页
作者
Zou J.; Xu Q.; Luo J.; Wang R.; Huang R.; Wang Y.;
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作者单位

Institute of Microelectronics, Peking University, Beijing, China;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
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1. Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs [J] . Zou J., Xu Q., Lou J., Electron Devices, IEEE Transactions on . 2011,第10期

机译：全方位栅极圆柱形硅纳米线MOSFET中寄生栅极电容的预测3-D建模
2. Temperature-Dependent Characteristics of Cylindrical Gate-All-Around Twin Silicon Nanowire MOSFETs (TSNWFETs) [J] . Keun Hwi Cho, Sung Dae Suk, Yun Young Yeoh, IEEE Electron Device Letters . 2007,第12期

机译：圆柱型全栅极双硅纳米线MOSFET（TSNWFET）的温度相关特性
3. Negative-Bias Temperature Instability in Gate-All-Around Silicon Nanowire MOSFETs: Characteristic Modeling and the Impact on Circuit Aging [J] . Liu C., Yu T., Wang R., Electron Devices, IEEE Transactions on . 2010,第12期

机译：全能栅极硅纳米线MOSFET的负偏压温度不稳定性：特性建模及其对电路老化的影响
4. 3-D modeling of fringing gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs [C] . An TaeYoon, Kim SoYoung International Conference on Simulation of Semiconductor Processes and Devices . 2013

机译：全方位栅圆柱形硅纳米线MOSFET边缘栅电容的3-D建模
5. Gate-All-Around Nanowire MOSFET for DNA Sequencing [D] . ?Islam, Mohammad Azharul 2020

机译：用于DNA测序的门 - 全部纳米线MOSFET
6. Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs [O] . Jie Gu, Qingzhu Zhang, Zhenhua Wu, 2021

机译：P型门 - 全面硅纳米线MOSFET的低温传输特性
7. Compact modeling of gate-all-around silicon nanowire MOSFETs [O] . Shihuan Lin -1

机译：门 - 全面硅纳米线MOSFET的紧凑型型号

Corrections to “Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs”

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