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Design of Novel 300-V Field-MOS FETs With Low on-Resistance for Analog Switch Circuits

机译:用于模拟开关电路的低导通电阻的新型300V场MOS FET的设计

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Novel 300-V Field-MOS FETs were developed for high-voltage analog switch circuits. The breakdown voltages of the Field-NMOS/PMOS FETs were 410 V/370 V with the specific on-resistance of 1850/11 000 $hbox{m}Omega cdot hbox{mm}^{^{rm 2}}$ . The vertical and lateral electric fields were both optimized to maximize the breakdown voltage over a wide range of substrate voltages; the device layout optimization included adjusting the silicon-on-insulator thickness and the use of a deep well and a field plate. A low specific on-resistance was obtained as a result of using an extended-drain layer, in addition to the potential linearity of the current pathway in the drift region. This technology can be applied to 300-V analog switch ICs that need to have a low leakage current and a low switching resistance.
机译:新型300V场MOS FET是为高压模拟开关电路开发的。场NMOS / PMOS FET的击穿电压为410 V / 370 V,比导通电阻为1850/11 000 $ hbox {m}Ωcdot hbox {mm} ^ {^ {rm 2}} $。垂直和横向电场均经过优化,可在很大范围的基板电压下使击穿电压最大化。器件布局的优化包括调整绝缘体上硅的厚度以及使用深阱和场板。除了漂移区中电流通路的电位线性以外,由于使用了漏极扩展层,因此还获得了较低的比导通电阻。该技术可以应用于需要低泄漏电流和低开关电阻的300V模拟开关IC。

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