Charge Trapping Model for Temporal Threshold Voltage Shift in a-IGZO TFTs Considering Variations of Carrier Density in Channel and Electric Field in Gate Insulator

摘要

A charge trapping model is proposed considering the variations of carrier density ( in the channel and electric field in the gate insulator (GI) of amorphous-InGaZnO thin-film transistors (TFTs) during the gate bias stress. When the trapped electron charge amount in the GI is large enough, and decrease. These changes weaken the hopping conduction of trapped electrons in gate oxide, and hinder the electron injection into the insulator, and thus slow down TFT threshold voltage shift ( rate. The resulted model predicts accurately degradation under gate bias stress, especially when the TFTs experience a long time and/or high voltage of electrical stress.