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首页> 外文期刊>Journal of Physics, D. Applied Physics: A Europhysics Journal >Abnormal threshold voltage shift caused by trapped holes under hot-carrier stress in a-IGZO TFTs
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Abnormal threshold voltage shift caused by trapped holes under hot-carrier stress in a-IGZO TFTs

机译:在A-IGZO TFT中的热载波应力下捕获孔引起的异常阈值电压移位

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In the investigation of the reliability of a back-channel-etching type amorphous InGaZnO thin film transistor, we found that hot carrier stress has caused an abnormal parallel negative threshold voltage shift in the I-D-V-G measurement. An electrical measurement method named drain stress was established to investigate this instability. Through the analysis of recovery behavior, gate bias stress and Silvaco simulation, we confirmed that holes from the drain side inject into the passivation layer and/or back-channel interface region rather than into the gate insulator under the transverse electric field. A physical model is proposed to verify this electrical degradation behavior. This work demonstrates that drain stress is valuable in examining the quality of the passivation layer in thin film transistors.
机译:在对后沟道蚀刻型无定形Ingazno薄膜晶体管的可靠性的研究中,我们发现热载体应力导致I-D-V-G测量中的异常并联负阈值电压移位。 建立了一个名为漏极应力的电测量方法来研究这种不稳定性。 通过分析恢复行为,栅极偏置应力和Silvaco模拟,我们确认从排水侧注入钝化层和/或后通道接口区域的孔,而不是在横向电场下进入栅极绝缘体。 提出了物理模型来验证这种电气劣化行为。 这项工作表明,在检查薄膜晶体管中的钝化层的质量时,漏极应力是有价值的。

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