机译:双门异质结隧道FET的紧凑模型
Key Laboratory of Integrated Microsystems, School of Electronic and Computer Engineering, Peking University Shenzhen Graduate School, Shenzhen, China;
Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong;
Key Laboratory of Integrated Microsystems, School of Electronic and Computer Engineering, Peking University Shenzhen Graduate School, Shenzhen, China;
Key Laboratory of Integrated Microsystems, School of Electronic and Computer Engineering, Peking University Shenzhen Graduate School, Shenzhen, China;
Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong;
Tunneling; Electric potential; Logic gates; Heterojunctions; Doping; Mathematical model; TFETs;
机译:SI1-XGEX / SI异质结双栅极隧道场效应晶体管(TFET)紧凑的电位模型
机译:基于二维物理的双栅极隧道FET的紧凑DC建模
机译:从源到漏的直接带间隧道效应引起的In-GaAs / GaAsSb异质结双栅隧道FET的缩放极限
机译:垂直隧道路径的inas-si异质结双栅隧道FET分析
机译:双栅极MOSFET的紧凑模型。
机译:具有InAs / Si异质结和源极口袋结构的双栅隧道FET的漏极电流模型
机译:对称双栅MOSFET的紧凑模型,包括载流子限制和短沟道效应