Reduction of leakage current at the gate edge of SDB SOI NMOS transistor

摘要

Leakage current through the parasitic channel formed at the sidewall of the SOI active region has been investigated by measuring the subthreshold I-V characteristics. Partially depleted (PD, /spl sim/2500 /spl Aring/) and fully depleted (FD, /spl sim/800 /spl Aring/) SOI NMOS transistors of enhancement mode have been fabricated using the silicon direct bonding (SDB) technology. Isolation processes for the SOI devices were LOCOS, LOCOS with channel stop ion implantation or fully recessed trench (FRT). The electron concentration of the parasitic channel is calculated by the PISCES IIb simulation. As a result, leakage current of the FD mode SOI device with FRT isolation at the front and back gate biases of 0 V was reduced to /spl sim/pA and no hump was seen on the drain current curve.