机译:65 nm nMOS晶体管中栅极泄漏电流的磁调制:实验,建模和仿真结果
National Institute for Astrophysics, Optics and Electronics (INAOE), Department of Electronics, L. E. Erro Nr. 1, Tonantzintla, Puebla, Z.P. 72000, Mexico;
rnNational Institute for Astrophysics, Optics and Electronics (INAOE), Department of Electronics, L. E. Erro Nr. 1, Tonantzintla, Puebla, Z.P. 72000, Mexico;
rnUniversidad Veracruzana, C. Ruiz-Cortines Nr. 455, Veracruz, Z.P. 561, Mexico;
rnUniversidad Veracruzana, C. Ruiz-Cortines Nr. 455, Veracruz, Z.P. 561, Mexico;
rnIBM Microelectronics, B-330C-1R23, Zip/20A 2070 Route 52, Hopewell Junction, NY 12533, USA;
65 nm MOSFET; gate leakage; magnetic field; em interference;
机译:减少SDB SOI NMOS晶体管栅极边缘的泄漏电流
机译:高电流脉冲下gg-nMOS晶体管的实验和3D仿真相关性
机译:高电流脉冲下gg-nMOS晶体管的实验和3D仿真相关性
机译:磁场在65nm nMOS晶体管中引起的栅极泄漏电流
机译:独立双栅极SOI MOSFET晶体管泄漏电流的仿真分析。
机译:门控电流谐波。二。轴突门控电流的模型仿真。
机译:NMOS晶体管的辐射引起的泄漏电流增加的参数化