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Accurate determination of ultrathin gate oxide thickness and effective polysilicon doping of CMOS devices

机译:准确确定CMOS器件的超薄栅氧化层厚度和有效多晶硅掺杂

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摘要

We present an efficient and accurate method to characterize the physical thickness of ultrathin gate oxides (down to 25 /spl Aring/) and the effective polysilicon doping of advanced CMOS devices. The method is based on the model for Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for the polysilicon-gate depletion. By fitting the model to measured data, both the gate oxide thickness and the effective poly doping are unambiguously determined. Unlike the traditional capacitance-voltage (C-V) technique that overestimates thin-oxide thickness and requires large area capacitor, this approach results in true physical thickness and the measurement can be performed on a standard sub-half micron transistor. The method is suitable for oxide thickness monitoring in manufacturing environments.
机译:我们提出了一种有效而准确的方法来表征超薄栅氧化物的物理厚度(低至25 / spl Aring /)以及先进CMOS器件的有效多晶硅掺杂。该方法基于Fowler-Nordheim(F-N)隧穿电流穿过栅极氧化物的模型,并通过对栅极电压进行校正以解决多晶硅栅极耗尽的问题。通过将模型拟合到测量数据,可以明确确定栅极氧化层厚度和有效多晶硅掺杂量。与传统的电容-电压(C-V)技术高估了薄氧化物的厚度并需要大面积的电容器不同,此方法可产生真实的物理厚度,并且可以在标准的半半微米晶体管上进行测量。该方法适用于制造环境中的氧化物厚度监测。

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