Ultrathin nitride/oxide (N/O) gate dielectrics for p/sup +/-polysilicon gated PMOSFETs prepared by a combined remote plasma enhanced CVD/thermal oxidation process

摘要

Ultrathin nitride-oxide (N/O/spl sim/1.5/2.6 nm) dual layer gate dielectrics have been incorporated into PMOSFETs with boron-implanted polysilicon gates. Boron penetration is effectively suppressed by the top plasma-deposited nitride layer leading to improved short channel performance as compared to PMOSFETs with oxide dielectrics. In addition, improved interface characteristics and hot carrier degradation immunity are also demonstrated for the devices with the N/O dual layer gate dielectrics.