Bonded Planar Double-Metal-Gate NMOS Transistors Down to 10 nm

摘要

BECAUSE of their optimal electrostatic channel control, multigate architectures allow the use of undoped channels, offering the opportunity to enhance carrier transport properties. In addition to suppressing poly depletion, metal gates also become essential to adjust threshold voltage (V{sub}(th)). Thanks to an original planar double-gate (DG) process based on bonding [1], we manage to integrate direct TiN metal gates on ultrathin undoped channels and to design low access resistances. Depending on channel thickness, 20-nm-gate-length transistors properties are tuned from high-performance (I{sub}(on) = 1250μA//μm for T{sub}(Si) = 10 nm) to low-power (I{sub}(off) = 0.9 nA/μm for T{sub}(Si) = 6 nm). For the thinnest channel thickness, we also demonstrate 10-nm transistors with I{sub}(on) = 1130μm/μA. This performance is comparable with recently published results on sub-10-nm Finfet and planar SOI [2]-[4] or metal-gate devices [4]-[7].