High-Performance Polysilicon TFTs Using Stacked Pr2O3/Oxynitride Gate Dielectric

摘要

In this letter, we have developed, for the first time, a stacked $ hbox{Pr}_{2}hbox{O}_{3}/hbox{SiO}_{x}hbox{N}_{y}$ gate dielectric into low-temperature polysilicon (poly-Si) thin-film transistors (TFTs). A high-performance TFT device that has a high effective carrier mobility, a high driving current, a small subthreshold swing, and a high $I_{rm ON}/I_{rm OFF}$ current ratio can be achieved. This phenomenon is attributed to the smooth $hbox{Pr}_{2}hbox{O}_{3}$/poly-Si interface provided by the $hbox{N}_{2}hbox{O}$ plasma treatment. The presence of the $hbox{SiO}_{x}hbox{N}_{y}$ buffer layer also enhanced the electrical reliability of the $hbox{Pr}_{2}hbox{O}_{3}$ poly-Si TFT. All of these results suggest that a high-$k$ $hbox{Pr}_{2}hbox{O}_{3}$ gate dielectric prepared under the buffer layer is a good candidate for high-performance TFTs.