Metal Floating Gate Memory Device With SiO₂/HfO₂ Dual-Layer as Engineered Tunneling Barrier

摘要

Metal as floating gate (FG) in combination with high-k dielectrics has been seen as a possible solution to continue the scaling of nand flash technology node beyond (2times ) nm. In this letter, it is demonstrated that stacked metal FG memory cell with SiO₂/HfO₂ dual-layer engineered tunneling barrier shows good memory characteristics. It presents favorable performance with lower operation voltage as well as enhanced program/erase speed. Furthermore, improvement of data retention is also obtained, proving that SiO₂/HfO₂ engineered tunnel barrier is promising for the improvement of metal FG memory performance.