SiO_2 tunneling and Si_3N_4/HfO_2 trapping layers formed with low temperature processes on gate-all-around junctionless charge-trapping flash memory devices

摘要

The SiO2tunneling and Si3N4/HfO2trapping layers formed with low temperature (LT) processes on operation characteristics of gate-all-around (GAA) junctionless (JL) charge trapping (CT) flash memory devices were studied in this work. The devices with an Ω-nanowire configuration were also compared. The faster operation speeds and larger memory windows are achieved by a GAA configuration. However, the worse retention characteristics for GAA devices may be caused by the SiO2and Si3N4layer with worse step coverage, which are formed by the LT processes. The coverage issues of dielectrics deposited with LT processes in GAA JL CT flash devices need solutions for 3D memory applications.