...
首页> 外文期刊>IEEE Electron Device Letters >Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study
【24h】

Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study

机译:负电容作为隧道FET和MOSFET的性能提升器:一项实验研究

获取原文
获取原文并翻译 | 示例
           

摘要

This letter reports for the first time a full experimental study of performance boosting of tunnel FETs (TFETs) and MOSFETs by negative capacitance (NC) effect. We discuss the importance of capacitance matching between a ferroelectric NC and a device capacitance to achieve hysteretic and non-hysteretic characteristics. PZT ferroelectric capacitors are connected to the gate of three terminals TFETs and MOSFETs and partial or full matching NC conditions for amplification and stability are obtained. First, we demonstrate the characteristics of hysteretic and non-hysteretic NC-TFETs. The main performance boosting is obtained for the non-hysteretic NC-TFET, where the ON-current is increased by a factor of 500 times, transconductance is enhanced by three orders of magnitude, and the low slope region is extended. The boosting of performance is moderate in the hysteretic NC-TFET. Second, we investigate the impact of the same NC booster on MOSFETs. Subthreshold swing as steep as 4 mV/decade with a 1.5-V hysteresis is obtained on a commercial device fabricated in 28-nm CMOS technology. Moreover, we demonstrate a non-hysteretic NC-MOSFET with a full matching of capacitances and a reduced subthreshold swing down to 20 mV/decade.
机译:这封信首次报告了通过负电容(NC)效应提高隧道FET(TFET)和MOSFET的性能的完整实验研究。我们讨论了铁电NC与器件电容之间实现电容匹配的重要性,以实现磁滞和非磁滞特性。 PZT铁电电容器连接到三个端子TFET和MOSFET的栅极,并获得了部分或完全匹配的NC条件,以实现放大和稳定性。首先,我们演示了磁滞和非磁滞NC-TFET的特性。非迟滞NC-TFET的主要性能得到了提高,其中导通电流增加了500倍,跨导提高了三个数量级,低斜率区域得到了扩展。在磁滞NC-TFET中,性能的提升适中。其次,我们研究了同一个NC升压器对MOSFET的影响。在采用28nm CMOS技术制造的商用设备上,亚阈值摆幅陡峭至4 mV /十倍,具有1.5V的迟滞。此外,我们展示了一种具有完全匹配电容和降低至20 mV /十倍的亚阈值摆幅的无磁滞NC-MOSFET。

著录项

  • 来源
    《IEEE Electron Device Letters》 |2017年第10期|1485-1488|共4页
  • 作者单位

    Laboratory of Micro and Nano-Electronic Devices, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland;

    Laboratory of Integrated Circuits, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland;

    Laboratory of Micro and Nano-Electronic Devices, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland;

    Laboratory of Micro and Nano-Electronic Devices, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland;

    Forschungszentrum Jülich, Peter Grünberg Institute 9 (PGI-9), Jülich, Germany;

    Forschungszentrum Jülich, Peter Grünberg Institute 9 (PGI-9), Jülich, Germany;

    Forschungszentrum Jülich, Peter Grünberg Institute 9 (PGI-9), Jülich, Germany;

    Laboratory of Integrated Circuits, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland;

    Laboratory of Micro and Nano-Electronic Devices, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Capacitance; Logic gates; MOSFET; TFETs; Capacitors; Boosting;

    机译:电容;逻辑门;MOSFET;TFET;电容器;升压;

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号