The design of an all-digital phase-locked loop with small DCOhardware and fast phase lock

摘要

The cores of the all-digital phase-locked loop (ADPLL) are thenswitch-tuning digital control oscillator (DCO) and the architecture, Innthis brief, we propose a DCO with reduced hardware cost, andnarchitecture with characteristics of fast frequency locking, fullndigitization, easy design and implementation, and good stability. It isnsuitable to be used as the clock generator for high-performancenmicroprocessors. The prototype of a 3.3-V ADPLL chip has been designednby TSMC's 0.6 Μm SPDM CMOS process. The simulation shows that thisnADPLL can operate in the range between 60 and 400 MHz, and at four timesnthe reference clock frequency. The phase-lock process takes 47 clockncycles, and the phase error is less than 0.1 ns