首页> 美国卫生研究院文献>Beilstein Journal of Nanotechnology >Quantitative comparison of wideband low-latency phase-locked loop circuit designs for high-speed frequency modulation atomic force microscopy
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Quantitative comparison of wideband low-latency phase-locked loop circuit designs for high-speed frequency modulation atomic force microscopy

机译:高速调频原子力显微镜的宽带低延迟锁相环电路设计的定量比较

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摘要

A phase-locked loop (PLL) circuit is the central component of frequency modulation atomic force microscopy (FM-AFM). However, its response speed is often insufficient, and limits the FM-AFM imaging speed. To overcome this issue, we propose a PLL design that enables high-speed FM-AFM. We discuss the main problems with the conventional PLL design and their possible solutions. In the conventional design, a low-pass filter with relatively high latency is used in the phase feedback loop, leading to a slow response of the PLL. In the proposed design, a phase detector with a low-latency high-pass filter is located outside the phase feedback loop, while a subtraction-based phase comparator with negligible latency is located inside the loop. This design minimizes the latency within the phase feedback loop and significantly improves the PLL response speed. In addition, we implemented PLLs with the conventional and proposed designs in the same field programmable gate array chip and quantitatively compared their performances. The results demonstrate that the performance of the proposed PLL is superior to that of the conventional PLL: 165 kHz bandwidth and 3.2 μs latency in water. Using this setup, we performed FM-AFM imaging of calcite dissolution in water at 0.5 s/frame with true atomic resolution. The high-speed and high-resolution imaging capabilities of the proposed design will enable a wide range of studies to be conducted on various atomic-scale dynamic phenomena at solid–liquid interfaces.
机译:锁相环(PLL)电路是调频原子力显微镜(FM-AFM)的核心组件。但是,其响应速度通常不足,并且限制了FM-AFM成像速度。为了克服这个问题,我们提出了一种可实现高速FM-AFM的PLL设计。我们讨论了常规PLL设计的主要问题及其可能的解决方案。在传统设计中,在相位反馈环路中使用了具有较高延迟的低通滤波器,导致PLL响应缓慢。在提出的设计中,具有低延迟高通滤波器的相位检测器位于相位反馈环路的外部,而具有可忽略的延迟的基于减法的相位比较器位于环路的内部。这种设计使相位反馈环路内的等待时间最小化,并显着提高了PLL响应速度。此外,我们在同一个现场可编程门阵列芯片中采用常规和建议的设计实现了PLL,并定量比较了它们的性能。结果表明,所提出的PLL的性能优于常规PLL:165 kHz带宽和水中3.2μs的延迟。使用此设置,我们以真实的原子分辨率以0.5 s /帧的频率对方解石进行了FM-AFM成像。拟议设计的高速和高分辨率成像能力将使人们能够对固液界面上的各种原子尺度的动力学现象进行广泛的研究。

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