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The frequency modulation method in a phase-locked loop circuit and phase-locked loop circuit

机译:锁相环电路中的调频方法及锁相环电路

摘要

The present invention provides a phase locked loop circuit comprising: a frequency divider for frequency-diving an output signal to generate frequency-divided pulses; an oscillator for generating the output signal under control to an oscillation frequency by a control voltage obtained from a signal corresponding to a phase difference between the frequency-divided pulses and a reference frequency signal; and a controller for performing such a control that plural kinds of frequency dividing rate are switched to be given to the frequency divider for every time period having a predetermined number of the frequency divided pulses, and at a boundary of switching the plural kinds of frequency dividing rate, the plural kinds of frequency dividing rate are given co-existentially to the frequency divider, and further for switching the coexistent plural kinds of the frequency-dividing rate, the next frequency dividing rate is given before a first appearance of a frequency peak in a transitional characteristic of the frequency of the clock signal outputted from the phase locked loop circuit caused by previous setting the frequency-dividing rate.
机译:本发明提供了一种锁相环电路,包括:分频器,用于对输出信号进行分频以产生分频的脉冲。振荡器,用于通过从与分频脉冲与参考频率信号之间的相位差相对应的信号获得的控制电压,在控制下将输出信号生成为振荡频率;控制器,该控制器进行控制,使得在具有预定数量的分频脉冲的每个时间段内,并且在切换多种分频的边界,切换多种分频率,以赋予分频器在此情况下,将多种分频率共存给分频器,并且为了切换多种分频率并存,在下一次出现频率峰值之前给出下一个分频率。由先前设置的分频率引起的从锁相环电路输出的时钟信号的频率的过渡特性。

著录项

  • 公开/公告号JP3389915B2

    专利类型

  • 公开/公告日2003-03-24

    原文格式PDF

  • 申请/专利权人 日本電気株式会社;

    申请/专利号JP20000059646

  • 发明设计人 岡 芳孝;

    申请日2000-03-03

  • 分类号H03L7/08;H03C3/00;H03L7/183;

  • 国家 JP

  • 入库时间 2022-08-22 00:21:36

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