A Phase-Locked Loop in High-Temperature Silicon Carbide and General Design Methods for Silicon Carbide Integrated Circuits.

摘要

Silicon carbide (SiC) has long been considered for integrated circuits (ICs). It offers several advantages, including wider temperature range, larger critical electric field, and greater radiation immunity with respect to Silicon (Si). At the same time, it suffers from challenges in fabrication consistency and lower transconductance which the designer must overcome. One of the recent SiC IC processes developed is the Raytheon High-Temperature Silicon Carbide (HTSiC) complementary MOSFET process. This process is one of the first to offer P channel MOSFETs and, as a result, a greater variety of circuits can be built in it.;The behavior of SiC MOSFETs has some important differences with Si MOSFETs. Models such as the Shichman-Hodges, EKV, and Short-channel models have been developed over time to address the important behaviors observed in Si MOSFETs, but none of these captures all of the important effects in SiC. In this work, an improved Shichman-Hodges model that incorporates the body-charge effect, mobility reduction, and a nonlinear channel modulation is developed for SiC CMOS IC devices. The importance of considering these effects is demonstrated with a simple design exercise.;This dissertation also describes the design and testing of the first-ever phase-locked loop (PLL) in SiC. This PLL is suitable for use as a general circuit building block such as in a clock recovery circuit. The fabricated circuit operates between 600 kHz and 1.5 MHz, and at temperatures up to 300. Testing results also show that output jitter and locking are negatively impacted at higher temperatures, and an improved design is proposed and analyzed.