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Adaptive Spur Cancellation Technique in All-Digital Phase-Locked Loops

机译:全数字锁相环中的自适应杂散消除技术

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The phenomenon of periodic phase errors (also known as spurs) in phase-locked loops (PLLs) is widely acknowledged and is responsible for posing considerable challenge on development of miniaturized wireless communication devices. The common approach employed today for spur mitigation calls for a digital notch filter within the receive chain, while there is no similar digital scheme for the transmit chain. In addition, this notch filter is not perfect and usually degrades the overall receiver sensitivity. This brief puts forward a novel idea, which is to cancel the spurs inside the PLL such that the local oscillator signal and consequently TX and RX antenna ports become spur-free. The technique is based on a least-mean squares algorithm that features a self-learning capability. The method has been silicon proven in a digital PLL of a transceiver radio test chip realized in a standard nanoscale CMOS technology.
机译:锁相环(PLL)中的周期性相位误差现象(也称为杂散)已得到广泛认可,并且对小型化无线通信设备的开发提出了相当大的挑战。如今,用于抑制杂散的常用方法要求在接收链中使用数字陷波滤波器,而对于发射链则没有类似的数字方案。另外,该陷波滤波器并不完美,通常会降低整体接收器的灵敏度。本简介提出了一种新颖的想法,即消除PLL内部的杂散,以使本地振荡器信号以及因此TX和RX天线端口变为无杂散。该技术基于具有自学习功能的最小均方算法。该方法已在以标准纳米级CMOS技术实现的收发器无线电测试芯片的数字PLL中经过硅验证。

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