首页> 外国专利> ADAPTIVE SPUR CANCELLATION TECHNIQUES AND MULTI-PHASE INJECTION LOCKED TDC FOR DIGITAL PHASE LOCKED LOOP CIRCUIT

ADAPTIVE SPUR CANCELLATION TECHNIQUES AND MULTI-PHASE INJECTION LOCKED TDC FOR DIGITAL PHASE LOCKED LOOP CIRCUIT

机译:数字锁相环的自适应脉冲取消技术和多相注入锁定TDC

摘要

A digital phase-locked loop includes a digital loop filter, a digitally controllable oscillator (DCO), and an injection-locked calibration-free time-to-digital converter (TDC) having a ring oscillator connected to the DCO via an input buffer that converts a sinusoidal DCO signal to a differential square wave signal provided to the ring oscillator such that ring oscillator frequency matches DCO frequency. A spur cancellation loop between the TDC and digital loop filter generates a spur cancellation signal based on an estimate of a spurious tone amplitude and phase. The spur cancellation signal is subtracted from TDC output signals prior to input to the digital loop filter. The spur cancellation loop may include a gradient descent strategy, or a feedforward strategy having a high-pass filter, integer delay chain, adaptive fractional delay, and signal averaging logic to cancel multiple internal and external spurs having frequencies that are not related to the reference clock frequency.
机译:数字锁相环包括一个数字环路滤波器,一个数字可控振荡器(DCO)和一个注入锁定免校准无时间数字转换器(TDC),该转换器具有通过输入缓冲器连接到DCO的环形振荡器。将正弦DCO信号转换为提供给环形振荡器的差分方波信号,以使环形振荡器频率与DCO频率匹配。 TDC和数字环路滤波器之间的杂散消除环路基于对寄生音调幅度和相位的估计来生成杂散消除信号。在输入到数字环路滤波器之前,先从TDC输出信号中减去杂散消除信号。杂散消除环路可以包括梯度下降策略或具有高通滤波器,整数延迟链,自适应分数延迟和信号平均逻辑的前馈策略,以消除频率与基准不相关的多个内部和外部杂散时钟频率。

著录项

  • 公开/公告号US2016359493A1

    专利类型

  • 公开/公告日2016-12-08

    原文格式PDF

  • 申请/专利权人 UNIVERSITY OF SOUTHERN CALIFORNIA;

    申请/专利号US201615170882

  • 发明设计人 SHUO-WEI CHEN;CHENG-RU HO;

    申请日2016-06-01

  • 分类号H03L7/099;H03L7/091;H03L7/093;

  • 国家 US

  • 入库时间 2022-08-21 13:43:30

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