基于Verilog的FPGA整数分频器设计及仿真

摘要

A brief introduction for the main clock division method was given,put forward limitations of FPGA internal PLL frequency divider,and gave the integer divide method based on Verilog HDL.Wrote Verilog HDL program,realized an arbitrary integer divider that the duty cycle is 50% and based on the hardware platform of the FPGA.Combined with Quartus development platform and Modelsim simulation software validation,the results showed that the frequency division method is simple and practical.By using this method,the replacement value of N can realize any integer frequency divider that duty cycle.%简单介绍了主要的时钟分频方法，提出了FPGA内部PLL分频的局限性，给出了基于 Ver-ilog HDL的整数分频方法。编写了Verilog HDL程序，实现了基于 FPGA 硬件平台的占空比为50%的任意整数分频。结合 Quartus开发平台和Modelsim仿真软件验证表明，该分频方法简单、实用。采用该方法，替换N值可实现任意整数等占空比的分频。