METHOD OF IMPLEMENTING IEC 61131-3 CONTROL SPECIFICATION ON FPGA DEVICES AS VERILOG HDL DESCRIPTION FOR EMULATION MODELING AND SIMULATION

摘要

The present invention relates to a method of implementing an IEC 61131-3 control specification through Verilog HDL description comprising the steps of (a) creating user interface for the control specification including languages covered under the IEC 61131-3, particularly ladder diagram, functional block diagram, sequential flow charts, structured text or instruction set listing; (b) generating a list of network interconnections with reference to the above referred languages; (c) generating logic equations using the aforesaid list of network interconnections generated at step (b) above; (d) generating Verilog HDL code snippets in accordance with the IEC 61131-3; (e) generating Verilog HDL code representing hardware with PLC functionality through said control specification by using the Verilog HDL code snippets generated at step (d), the logic equations at step (c) and the network interconnections at step (b).