SYSTEM AND METHOD FOR EMULATION AND SIMULATION OF RTL (DESIGN UNDER TEST) USING FPGA

摘要

The disclosure relates to a system and method for emulation and simulation of RTL (DUT) using FPGA. In one embodiment, a text based RTL design is converted into emulation capable RTL design which is then synthesized to generate a bit file using an EDA. The bit file is then loaded into the on-board FPGA and test cases are injected to the design under test (DUT) using a transactor, and at every clock cycle, the flip-flops states of the FPGA are recorded in a memory module. A simulation file is generated by mapping resultant states of the flip-flops with their naming nomenclature from the text based RTL design. The system provides a user friendly GUI using which a user/designer may choose debugging capabilities at modular level or for the complete IP core.