基于CMOS多功能数字芯片的ESD保护电路设计

摘要

An ESD protection circuit is designed based on CSMC 2P2M 0.6 μm CMOS process.The circuit is simulated using Hspice and the process of the CSMC 2P2M 0.6 μm CMOS（06 mixddct02v24）,the layout is based on CSMC 2P2M 0.6 μm CMOS and is used in a Multi-functional Digital Chip.The chip area is 1 mm×1 mm.The design has been successfully implemented by participating in the plan of the Multi Project Wafer.Measurements indicate that the wafer achieves the expected goals.%基于CSMC 2P2M 0.6μm CMOS工艺设计了一种ESD保护电路。整体电路采用Hspice和CSMC 2P2M的0.6μm CMOS工艺的工艺库（06mixddct02v24）仿真,基于CSMC 2P2M 0.6μm CMOS工艺完成版图设计,并在一款多功能数字芯片上使用,版图面积为1 mm×1 mm,参与MPW（多项目晶圆）计划流片,流片测试结果表明,芯片满足设计目标。