基于FPGA的除法器设计

摘要

除法器是数字信号处理领域中最基本也是最复杂的运算单元.目前除法器的设计多采用迭代算法实现,实时性很差.为了提高除法器的实时性,文章基于线性逼近算法和ROM查找表相结合的方式,提出一种数字复数除法器的实现方法.相对于传统的数字除法器,它不但资源少,计算速度快,而且还可以根据修改ROM的数值精度来满足不同的性能要求,灵括性很高,在数字信号处理领域有广泛的应用和推广价值.%Divider is not only the most common, but also the most complex component in digital signal domain. It's used to use the iterative algorithm to implement it, and has lower real-time. To improve the real-time,this paper introduces a design of the digital complex divider which based on linear approximation algorithm and ROM look-up table. Compared to the traditional method, it not only has the less resource and the fast speed, but also can meet more flexible performance requirement with modifying the data precision stored in the ROM, so it has a widely application in digital signal process domain.