FPGA DESIGN ASSISTANCE SYSTEM, FPGA DESIGN ASSISTANCE METHOD, AND FPGA DESIGN ASSISTANCE PROGRAM

摘要

An FPGA design assistance system with which the SER when TMR is applied to a user circuit can be estimated in the FPGA design stage. This system has: a TMR effectiveness information DB that holds information that includes the SER reduction rate when TMR is applied; a CRAM_SER calculation unit that calculates the SER for the entire CRAM possessed by the FPGA; an FPGA resource usage rate calculation unit that calculates the FPGA resource usage rate for each circuit block; a circuit block SER calculation unit that calculates the SER in units of circuit blocks, on the basis of the SER for the entire CRAM and the FPGA resource usage rate for each circuit block; a TMR block SER calculation unit which, on the basis of the SER and the SER reduction rate when TMR is applied for the TMR blocks, calculates the SER for TMR blocks; and a SER calculation unit that calculates the SER for the entire user circuit on the basis of the SER for each circuit block and the SER for each TMR block.