As silicon CMOS devices are scaled down to the nanometer regime, the signal delay and power consumption caused by metal interconnects have become increasingly important factors limiting the overall performance of integrated circuits (ICs). By stacking the circuits in the vertical direction, we can reduce the number and length of interconnects as well as integrating more functionalities on one chip. One of the major challenges in fabricating monolithic three-dimensional ICs (3D-ICs) is that when processing the upper layers of devices we cannot raise the temperature of the underlying metal interconnects above 400 °C. Germanium-on-insulator (GeOI) MOSFETs have become promising for monolithic 3D-ICs owing to their low processing temperatures. In this work, we will present our studies on the rapid melt growth (RMG) method, which was invented by the Plummer group at Stanford University in 2003, and its application in the fabrication of high-performance GeOI MOSFETs for monolithic 3D-ICs.;Using simulations incorporating undercooling and random nucleation, we have analyzed the RMG process with Ge film thicknesses between 5 nm and 200 nm and buried oxide thicknesses between 100 nm and 500 nm. The minimum temperature in the liquid Ge is less than 1 K below the melting point. In this temperature range, the random nucleation probability is extremely small and no nucleation events occur in the simulation, which agrees well with our previous experimental results and explains why we can obtain GeOI with high crystal quality by RMG. The release of latent heat at the growth front raises the temperature here to only about 0.1 K below the melting point. Thus the growth rate is on the order of centimeters per second, which is comparable to the maximum pulling rate of the Czochralski (CZ) growth of an ingot with a comparable diameter.;Then the RMG method is extended to 3D-IC fabrication with laser annealing as the heating source, which can melt Ge while avoiding heating the underlying metal interconnects above 400 °C. We have studied three schemes of laser annealing, namely excimer laser annealing, scanning pulsed laser annealing, and scanning continuous-wave (CW) laser annealing. Numerical analysis is used to simulate the melting and crystallization processes as well as the temperature in the underlying Al interconnect. We have carried out experiments to study these laser annealing schemes. Among them, scanning CW laser annealing is found to be the most promising in producing ultra-long high-quality single-crystalline GeOI stripes.;Finally, the fabrication of high-performance GeOI MOSFETs is studied by experiment. We have demonstrated the monolithic integration of GeOI p-FETs with bulk Si n-FETs based the RMG method. In order to solve the problem of high source-to-drain leakage current, we have fabricated GeOI FinFETs and gate-all-around (GAA) MOSFETs. The experimental results show that the leakage current is caused by the interface traps at the Ge/buried oxide interface and that it can be mitigated by passivating and gate-controlling all the surfaces of the Ge stripe in the channel region. The leakage current has been successfully reduced, leading to 4 orders of magnitude improvement on the on/off ratio, and a subthreshold swing of 71 mV/dec has been obtained. In the GAA MOSFET experiments, we have also studied low-temperature device processes for monolithic 3D-ICs.
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