Advanced technology for source drain resistance reduction in nanoscale FinFETs.

摘要

Dual gate MOSFET structures such as FinFETs are widely regarded as the most promising option for continued scaling of silicon based transistors after 2010. This work examines key process modules that enable reduction of both device area and fin width beyond requirements for the 16nm node. Because aggressively scaled FinFET structures suffer significantly degraded device performance due to large source/drain series resistance (RS/D), several methods to mitigate RS/D such as maximizing contact area, silicide engineering, and epitaxially raised S/D have been evaluated.