首页> 外文会议>Symposium Proceedings vol.913; Symposium on Transistor Scaling-Methods, Materials and Modeling; 20060418-19; San Francisco,CA(US) >Schottky-Barrier Height Tuning Using Dopant Segregation in Schottky-Barrier MOSFETs on Fully-Depleted SOI
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Schottky-Barrier Height Tuning Using Dopant Segregation in Schottky-Barrier MOSFETs on Fully-Depleted SOI

机译:在完全耗尽的SOI上使用肖特基势垒MOSFET中的杂质隔离进行肖特基势垒高度调整

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In this paper we demonstrate the use of dopant segregation during silicidation for reducing the effective potential barrier height in Schottky-barrier metal-oxide-semiconductor field-effect-transistors (SB-MOSFETs). N-type as well as p-type devices are fabricated with arsenic/boron implanted into the device's source and drain regions prior to silicidation. During full nickel silicidation a highly doped interface layer is created due to dopants segregating at the silicide-silicon interface. This doped layer leads to an increased tunneling probability through the Schottky barrier and hence leads to significantly improved device characteristics. In addition, we show with simulations that employing ultrathin body (UTB) silicon-on-insulator and ultrathin gate oxides allows to further improve the device characteristics.
机译:在本文中,我们证明了在硅化过程中使用掺杂剂隔离可降低肖特基势垒金属氧化物半导体场效应晶体管(SB-MOSFET)的有效势垒高度。 N型和p型器件的制造是在硅化之前将砷/硼注入到器件的源极和漏极区中。在完全硅化镍的过程中,由于掺杂剂在硅化物-硅界面处偏析而形成了高掺杂界面层。该掺杂层导致通过肖特基势垒的隧穿可能性增加,因此导致器件特性得到显着改善。此外,我们通过仿真显示,采用超薄体(UTB)绝缘体上硅和超薄栅极氧化物可以进一步改善器件特性。

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