Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits

机译：闩锁测试在高压CMOS集成电路中引起的骤回故障机理

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An electrical overstress failure induced by a latch-up test is studied in high-voltage integrated cricuits. The latchup test resulted in damage to the output NMOSFET due to snapbach and also resulted in a latch-up in the internal circuits. These mechanism

机译：在高压集成十字路口中研究了由闩锁测试引起的电气过应力故障。闩锁测试由于snapbach导致输出NMOSFET损坏，并且还导致内部电路闩锁。这些机制

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来源
《Programmable Logic, 2008 4th Southern Conference on; Phoenix,AZ,USA》||P.625-626|共2页
会议地点 PhoenixAZUSA
作者
Jen-Chou Tseng; Yu-Lin Chen; Chung-Ti Hsu; Fu-Yi Tsai; Po-An Chen; Ming-Dou Ker;
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原文格式 PDF
正文语种 eng
中图分类工业技术;
关键词
CMOS integrated circuits; flip-flops; NMOSFET; electrical overstress failure; high-voltage CMOS integrated circuits; high-voltage integrated cricuits; latch-up test; snapback failure; EOS; ESD; high-voltage; latch-up;

机译：CMOS集成电路;触发器; NMOSFET;电气过应力故障;高压CMOS集成电路;高压集成电路;闩锁测试;快照故障; EOS; ESD;高压;闩锁;

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专利

1. Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by Latchup Test in a High-Voltage Integrated Circuits [J] . IEEE transactions on device and materials reliability . 2014,第1期

机译：防止高压集成电路中的闩锁测试引起的EOS故障的布局考虑和电路解决方案
2. Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product [J] . I-Cheng Lin, Chih-Yao Huang, Chuan-Jane Chao, Microelectronics & Reliability . 2003,第8期

机译：高压CMOS IC产品中的片上ESD保护电路引起的异常闩锁故障
3. THEORETICAL MODELS FOR MICROWAVE PULSE INDUCED THERMAL FAILURE IN CMOS INTEGRATED CIRCUITS [J] . Jie Chen, Zhengwei Du Microwave and optical technology letters . 2014,第5期

机译：CMOS集成电路中微波脉冲引起的热失效的理论模型
4. Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits [C] . Jen-Chou Tseng, Yu-Lin Chen, Chung-Ti Hsu, IEEE International Reliability Physics Symposium . 2008

机译：高压CMOS集成电路中闩锁测试引起的旋转响应失效机制
5. THE PHYSICS AND MODELING OF LATCH-UP AND CMOS INTEGRATED CIRCUITS [D] . ESTREICH, DONALD BRUCE. 1981

机译：闩锁和CMOS集成电路的物理和建模
6. A 180-Vpp Integrated Linear Amplifier for Ultrasonic Imaging Applications in a High-Voltage CMOS SOI Technology [O] . Kexu Sun, Zheng Gao, Ping Gui, -1

机译：180Vpp集成线性放大器用于高压CMOS SOI技术中的超声成像应用
7. Latch-Up Control in CMOS Integrated Circuits [O] . A. Ochoa, W. Dawes, D. Estreich 1979

机译：CMOS集成电路中的锁存控制
8. Latch-Up and Radiation Integrated Circuit--LURIC: A Test Chip for CMOS Latch-Up Investigation. [R] . estreich, d. b. 1978

机译：闩锁和辐射集成电路 - LURIC：用于CmOs闩锁调查的测试芯片。

Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits

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