Alternated Phase Shift Mask for 45nm Node Contact Holes Patterning

摘要

Among other memory products FLASHes are becoming a technology driver in term of design rules aggressiveness for dense structures. Upcoming revisions of ITRS roadmap forecast 45nm technology node introduction for FLASHes one year ahead (2006) compared to DRAMs (2007). In this scenario the basic development of 45nm process requires patterned samples starting from the end of 2005. Waiting for hyper-high NA ArF immersion tools availability, different RET solutions based on the existing lithography platforms have been evaluated with the aim to provide patterned samples for process modules development. Our paper is focused on 45nm node contact holes, certainly considered one of the most challenging layers in the technology assessment: various RET strategies will be briefly discussed and particular attention will be dedicated to alternating phase shift mask option. Strong PSM approach has been already proposed in the past as viable solution for 65nm node contact holes patterning using ArF tools; here we discuss problems related to its extension down to 45nm node (with dry equipments), in ultra low k_1 regime and close to the physical limit of 0.25 k_1. The paper addresses main challenges related to the application of an alt-PSM approach to a full-chip FLASH design, suggesting possible solutions for assist features generation and phase assignment. Different strategies to compensate for the well known phase imbalance phenomena have been selected by using fully rigorous 3D optical simulations. Finally preliminary printing test will be shown. Lithography performances (Minimum resolution, Process window, contact profile) will be compared with conventional RET techniques.