Compensating process non-uniformity to improve wafer Overlay by RegC®

摘要

The introduction of double and triple patterning tightened the Overlay current nodes' specifications across the industry to levels of 5nm and 3nm respectively. Overlay error is a combination of Intra-field and field-to-field errors. The Intra-field error includes several systematic signatures, such as overlay magnitude differences between X and Y axes, field center vs edge and more. The recent developments in scanner technology improved the intra-field Overlay to high orders. In this work we have quantified the state-of-the-art residual overlay errors and applied the RegC® (registration/overlay control) process, a new solution of deep sub-nanometer pattern shift, to further improve the overlay process control, in addition to the current lithography's state-of-the-art capabilities. As a result we managed to reduce the baseline overlay error by more than one nanometer and reduced systematic intra-field non-uniformities, by removing the 3 sigma difference between X and Y to zero. The combination of intra-field control by RegC® with high order correction per exposure (CPE) by the scanner provides a new era of overlay control required for the 2x and 1x multiple patterning processes.