首页> 外国专利> WAFER PROCESSING METHOD FOR GUARANTEEING OVERLAYER SI TO KEEP PERFECT QUALITY IN 3-DIMENSIONAL IC INTERGRATION

WAFER PROCESSING METHOD FOR GUARANTEEING OVERLAYER SI TO KEEP PERFECT QUALITY IN 3-DIMENSIONAL IC INTERGRATION

机译:晶片叠层的晶片加工方法,可确保3维IC集成中的完美质量

摘要

PURPOSE: A wafer processing method for guaranteeing overlayer Si to maintain perfect quality in 3-dimensional IC intergration is provided to keep initial process state or quality by eliminating small cracks and chipping at the edge of an upper layer wafer. CONSTITUTION: A PMD oxide film is formed on a lower layer substrate(S501). The contact is formed (S503). The first metal wiring is formed in the front of the lower layer substrate(S505). The oxide film is laminated in the front of the lower layer substrate(S507). The through-via hole is formed in the front of the lower layer substrate(S509). The second metal wiring is formed in the front of the lower layer substrate(S511). The second metal wiring is formed in the front of the lower layer substrate(S511). The nitride film or the oxide film is lamintaed in the front of the lower layer substrate(S515). The lower layer substrate is bonded with the upper layer wafer(S517). The upper layer wafer is bevel-etched(S523). The wafer alignment is formed(S525). The three-dimensional integrated circuit is integrated.
机译:目的:提供一种晶片处理方法,以确保上层硅在3D IC集成中保持完美的质量,从而通过消除小裂纹和上层晶片边缘的碎裂来保持初始工艺状态或质量。组成:在下层基板上形成PMD氧化膜(S501)。形成接触(S503)。在下层基板的前面形成第一金属布线(S505)。将氧化物膜层压在下层基板的前面(S507)。贯通孔形成在下层基板的前面(S509)。在下层基板的前面形成第二金属布线(S511)。在下层基板的前面形成第二金属布线(S511)。在下层基板的正面层叠氮化膜或氧化膜(S515)。将下层基板与上层晶片接合(S517)。对上层晶片进行斜角蚀刻(S523)。形成晶片对准(S525)。三维集成电路被集成。

著录项

  • 公开/公告号KR20100019907A

    专利类型

  • 公开/公告日2010-02-19

    原文格式PDF

  • 申请/专利号KR20080078662

  • 发明设计人 LEE WAN GYU;

    申请日2008-08-11

  • 分类号H01L21/027;H01L21/302;

  • 国家 KR

  • 入库时间 2022-08-21 18:33:15

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