Zero Delay Buffer (ZDB) PLLs have low Long Term Jitter (LTJ) requirements and demand a wide frequency range VCO design. This paper describes an "auto-ranging" technique that dynamically switches between different frequency ranges to overcome the tuning range limitation of a typical Voltage Controlled Oscillator (VCO). This allows a more stable loop, much tighter control over VCO gain (K_(VCO)) and consequently, improved (at least 2x achievable) LTJ performance. A number of high-performance applications require Phase-Locked-Loops (PLLs) that can achieve phase lock in times less than 1μs. To achieve these lock times special circuitry is required. This paper describes a PLL with a lock-aid circuit that achieves best-in-class lock times. The PLL has been designed in 135nm CMOS technology and illustrates the value of novel digital add-on circuits for PLLs in small feature size technologies.
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