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Output-jitter performance of second-order digital bang-bang phase-locked loops with nonaccumulative reference clock jitter

机译:具有非累积参考时钟抖动的二阶数字Bang-bang锁相环的输出抖动性能

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摘要

Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear systems due to the binary phase detector (BPD). While they are typically used for clock and data recovery, the ongoing trend toward digital loop implementations has resulted in several digital BBPLLs (DBBPLLs) suitable for frequency synthesis. This brief investigates the effect of nonaccumulative reference clock jitter (due to white phase noise) in second-order DBBPLLs, comparing the output jitter with that of first-order DBBPLLs. For small clock jitter, the nonlinear loop behavior is modeled as a two-dimensional Markov chain, and the output jitter is smaller than but close to that of a first order loop. For large clock jitter, the BPD nonlinearity is linearized, and the output jitter is larger than that of a first order loop; it is proportional to clock jitter and inversely proportional to the square root of the stability factor—the ratio of the proportional path gain to the integral-path gain of the digital loop filter.
机译:由于二进制相位检测器(BPD),Bang-bang锁相环(BBPLL)本质上是非线性系统。尽管它们通常用于时钟和数据恢复,但数字环路实现的持续趋势导致出现了几种适用于频率合成的数字BBPLL(DBBPLL)。本文简要研究了二阶DBBPLL中非累积基准时钟抖动(由于白相噪声)的影响,将输出抖动与一阶DBBPLL的输出抖动进行了比较。对于小时钟抖动,非线性环路行为被建模为二维马尔可夫链,并且输出抖动小于但接近于一阶环路。对于大的时钟抖动,BPD非线性度被线性化,并且输出抖动大于一阶环路。它与时钟抖动成正比,与稳定度的平方根成反比。稳定度是数字环路滤波器的比例路径增益与积分路径增益之比。

著录项

  • 作者

    Tertinek Stefan; Feely Orla;

  • 作者单位
  • 年度 2011
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  • 原文格式 PDF
  • 正文语种 {"code":"en","name":"English","id":9}
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