A Novel Ultra-Low Power and PDP 8T Full Adder Design Using Bias Voltage

摘要

Full adder circuit is one of the most important digital functional block used in ALU. This paper presents a novel design of 8T full adder. The 8T full adder is designed on basis of a new logic 3T XOR and 2:1 multiplexer, in total of 8T.Compared to other existing full adders of 10T, 14T. There is significant improvement in power consumption, delay and power-delay product. For a supply voltage of 1V the power obtained is 0.382pW, delay is 0.7932ps and a power-delay product is 0.303YJ. The analysis shows that the proposed circuit has ultra lowest power and power-delay product. The circuit is designed using the Cadence-virtuoso tool with 45nm technology.