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机译:超低功耗32位流水线加法器,采用亚阈值源耦合逻辑和5fJ /级PDP
Microelectronic Systems Laboratory (ISM), Ecole Polytechnique Federate de Lausanne (EPFL), 1015 Lausanne, Switzerland;
Electrical Engineering Department, Northern Arizona University, Flagstaff, AZ 86011, USA;
Microelectronic Systems Laboratory (ISM), Ecole Polytechnique Federate de Lausanne (EPFL), 1015 Lausanne, Switzerland;
CMOS integrated circuits; ultra-low power circuit design; source-coupled logic (SCL); current-mode logic (CML); subthreshold SCL (STSCL); pipelined SCL;
机译:超低功耗应用的亚阈值源耦合逻辑电路
机译:用于32位流水线Mips处理器的低功耗多模加法器的设计
机译:利用新型PMOS负载器件的超低功耗亚阈值电流模式逻辑
机译:在45nm FinFET的亚阈值电压下工作的超低功耗32位加法器的设计
机译:容错触发器设计用于超低功耗亚阈值逻辑。
机译:使用具有5FJ /级PDP的超低功耗32位流水线加法器,使用亚阈值源耦合逻辑