3D-WAFER LEVEL PACKAGING FOR MEMS BY USING A VIA MIDDLE APPROACH BASED ON COPPER THROUGH SILICON VIAS COMBINED WITH COPPER THERMO-COMPRESSION BONDING

摘要

A Cu based Technology for 3D-Wafer Level Packaging of Micro Electro Mechanical Systems (MEMS) is described. The approach is based on the combination of Through Silicon Vias (TSVs) and Thermo-Compression Bonding. In particular, TSVs are fabricated as blind vias into the cap wafer and revealed after bonding to the MEMS wafer. A conformal pattern plating method has been developed in order to metallise the TSVs and bonding frames in one step. Different pre-treatment methods have been tested regarding the achieved bonding strength. Further analysis includes cross sectional preparation and electrical continuity tests on the TSVs. A MEMS-dummy has been built to demonstrate the approach for two different TSV depths (80 μm and 160 μm).