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Underfill material Screening and Process Characterization for 3D Stacking

机译:3D堆叠的底部填充材料筛选和过程表征

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With the current development of IC technology nodes becoming "Moore-than-Moore" challenging, industry and research institutes such as Imec are increasing their focus to come up with solutions to these challenges. A solution closely followed at the moment is the development of 3D ICs and 3D packaging. In developing these technologies, there are quite a lot of complexities involved. The development and scaling of TSVs and micro-bumps, the handling of ultra thinned wafers, the stacking options needed and the selection of the right type of underfill material are widely considered as main challenges for 3D IC technology. In this paper we report on the activities for underfill development. The underfill material is one of the most critical parts of standard flip chip package and will also be a critical component for 3D stacks and packages. The selection of the right material is fundamental to ensure the reliability and cost effectiveness of both the 3D stack and package. Currently most of the underfill materials for 3D stacking are still under development, it is therefore important to evaluate, screen and develop such materials. A close collaboration with industry partners, material vendors, equipment vendors and chip manufacturers (FAB and Packaging) will hasten the development of these materials. In this paper, we will show the underfill screening methodology used at Imec and the criteria used to judge the effectiveness of the materials. The report will mainly cover 2 types of underfill materials, namely, No Flow Underfills and Wafer Level Underfills. Both underfill materials can be applied on die or at wafer level. Reliability, electrical testing, SAM inspection and cross-section results will also be presented. The materials are ranked based on the criteria and results gathered for the DoEs performed. The lessons learned based on the materials' characteristics will be discussed and may be considered as guidelines for selecting a specific material a particular 3D stacks or packages.
机译:随着IC技术节点的目前发展成为“摩尔比摩尔”挑战,工业和研究机构,如IMEC正在增加他们的重点来提出这些挑战的解决方案。目前紧随其后的解决方案是3D IC和3D包装的发展。在开发这些技术时,涉及了很多复杂性。 TSV和微凸块的开发和缩放,超薄晶片的处理,所需的堆叠选项以及正确类型的底部填充材料的选择被广泛被认为是3D IC技术的主要挑战。在本文中,我们报告了欠缺发展的活动。底部填充材料是标准倒装芯片封装最关键的部分之一,也将是3D堆叠和包装的关键组件。正确的材料选择是基本的,以确保3D堆叠和包装的可靠性和成本效益。目前大多数用于3D堆叠的底部填充材料仍在开发中,因此评估,屏幕和发展这些材料是很重要的。与行业合作伙伴,材料供应商,设备供应商和芯片制造商(FAB和包装)密切合作将加速这些材料的发展。在本文中,我们将显示IMEC中使用的底部填充筛选方法,以及用于判断材料有效性的标准。该报告主要涵盖2种类型的底部填充材料,即没有流量底部填充和晶圆底部填充物。底部填充材料都可以应用于模具或晶片水平。还将提供可靠性,电气测试,SAM检测和横截面结果。基于所执行的确实收集的标准,这些材料排序。将讨论基于材料特征的教训,并且可以被视为用于选择特定的3D堆叠或包装的特定材料的指导方针。

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