ESD event simulation automation using automatic extraction of the relevant portion of a full chip

摘要

An ESD SPICE simulation design analysis flow for a diverse design environment is introduced. Since the complexities of today's integrated circuits often make full chip transient simulations impractical and in many cases even impossible, this flow includes the automatic extraction of the relevant devices for a given ESD stress. An additional challenge is posed by the high number of simulations required for a comprehensive ESD analysis. To obtain timely results and cater for all required stress pin combinations, the simulations are run in parallel in a compute farm environment. For small to medium designs, a complete ESD performance assessment is typically available within several hours.