ESD full chip simulation: HBM and CDM requirements and simulation approach

摘要

Verification of ESD safety on full chip level is a majorchallenge for IC design. Especially phenomena with their origin in theoverall product setup are posing a hurdle on the way to ESD safe products.For stress according to the Charged Device Model (CDM), a stumbling stone fora simulation based analysis is the complex current distribution among a hugenumber of internal nodes leading to hardly predictable voltage drops insidethe circuits.This paper describes an methodology for Human Body Model(HBM) simulations with an improved ESD-failure coverage and a novelmethodology to replace capacitive nodes within a resistive network by currentsources for CDM simulation. This enables a highly efficient DC simulationclearly marking CDM relevant design weaknesses allowing for application ofthis software both during product development and for product verification.