ENHANCING THE RELIABILITY OF 3D PACKAGE BY ANALYZING CRACK BEHAVIOR ON TSV THROUGH STRUCTURAL OPTIMIZATION AND COMPARING MATERIAL PROPERTIES OF THE PACKAGE

摘要

As computing and communication devices are converging with improvement of the functionally which creates complexity of circuit interconnections for 2-D devices becomes a limitation for performance and drives up power dissipation. 3D through-silicon via (TSV) is the key to 3D integration and stacking of chips, is emerging now as a powerful tool to converge the demands of integrated circuit (IC) packages. In 3D TSV the chips are stacked on top of another so heat trapped in a small region which is difficult to dissipate that may cause failures in electronic devices. In this study, the effect of the optimization of package structure on the enhancement of the reliability of 3D package has been studied. Stress intensity factor, which indicates the state of stress has been analyzed with the change of die thickness for different positions on TSV and J-integral has been used to specify the crack driving force. An optimized structure of 3D TSV is designed to minimize the crack driving energy in the TSV region. Varying the thickness of die the crack is modeled on TSV which is studied during the chip attachment process. Finite element methods have been used to examine the thermo-mechanical stresses and fracture parameters of the structure of 3D TSV package Under Retlow condition the optimization of the structure of the package is taken place to make it more reliable. The materials used for TSV and solder bumps are another important factor to enhance package reliability. Comparisons of material properties are included in the result to show how it can impact the package reliability .