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LIFE PREDICTION AND DAMAGE EQUIVALENCY FOR SHOCK SURVIVABILITY OF ELECTRONIC COMPONENTS

机译:电子元件休克存活性的寿命预测和损伤等效

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There is a fundamental need for development of predictive techniques for electronic failure mechanisms in shock and drop-impact. Presently, one of the primary methodologies for assessment of shock and vibration survivability of electronic packaging is the JEDEC drop test method, JESD22-B111 which tests board-level reliability of packaging. However, packages in electronic products may be subjected to a widearray of boundary conditions beyond those targeted in the test method. Development of damage-equivalency methodologies will be invaluable in correlating standard test conditions to widely varying design-use conditions. In this paper, the development of a solder-joint stress based relative damage index has been investigated to establish a method for damage equivalency. Modal Analysis, Wavelet Decomposition, and Explicit Finite Element analysis has been used to assess reliability performance of the electronic boards. Deformation kinematics have been measured with the help of ultra high-speed data acquisition and video systems. Experimental data has been correlated to the finite element models. Failure predictions along with their modes and mechanisms have been discussed. Damage proxies for failure mechanisms in first-level interconnects have been developed. The approach is scalable to a wide variety of electronic applications. Component types examined include, plastic ball-grid arrays, flex ball-grid arrays for various pitch sizes between 0.5 mm to 1mm in both 63Sn37Pb and 95.5Sn4.0Ag0.5Cu solder alloy compositions. Dynamic measurements like acceleration, strain and resistance are measured and analyzed using highspeed data acquisition system capable of capturing in-situ strain, continuity and acceleration data in excess of 5 million samples per second. Ultra high-speed video upto 50,000 fps has been used to capture the deformation kinematics. Experimental results are correlated with finite element models which include reduced integration element formulations.
机译:对休克和抗冲击机制中的电子故障机制的预测技术的发展有基本需求。目前,用于评估电子包装的冲击和振动能力的主要方法之一是JEDEC DROP测试方法,JESD22-B111测试了包装板级可靠性。然而,电子产品中的包裹可以受到在测试方法中靶向的边界条件的宽阔率。在将标准测试条件相关到广泛不同的设计使用条件下,损坏等效方法的开发将非常宝贵。本文研究了焊接关节应力的相对损伤指数的发展,建立了损坏等效的方法。模态分析,小波分解和显式有限元分析已被用于评估电子板的可靠性性能。通过超高速数据采集和视频系统的帮助来测量变形运动学。实验数据与有限元模型相关联。已经讨论了失败预测以及它们的模式和机制。已经开发出第一级互连中的故障机制损坏代理。该方法可扩展到各种电子应用。检查组件类型包括塑料球栅阵列,塑料球栅阵列,各种俯仰尺寸在63SN37PB和95.5SN4.0AG0.5CU焊料合金组合物中0.5毫米至1mm。像加速度,应变和电阻动态测量被测量,并且使用高速能够在超过每秒500万个样品中原位捕获应变,连续性和加速度数据的数据采集系统进行分析。超高速视频高达50,000 FPS已用于捕获变形运动学。实验结果与有限元模型相关,其包括减少的整合元件配方。

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