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CIRRUS: FINE PITCH FLIP CHIP INTERCONNECT

机译:Cirrus:细间距倒装芯片互连

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As part of the European Project "Cirrus", an ultra thin IC package has been developed. The package, in the shape of a "cavity-down" Ultra Thin EGA, has 168 IOs and measures 9*9 mm. The interposer is 50 μm thick polyimide flex provided with a fan-out build with a Cu/Ni/Au stack. For the present design an IC of 5*5 mm has been used with a bondpad pitch of 100 μm. The package has a standardised board interface with ball pitch of 0.5 mm. The ultimate height reduction has been achieved through the use of a thinned die (150 μm) with low flip chip bumps (20 micron) in combination with anisotropic conductive adhesives. The resulting height after solder reflow on the motherboard is limited to 300 μm. In the paper the design, process investigations for first level and coplanarity requirements for the second level interconnect will be treated. Further work is aimed at realising the chip connection to the foil using a lead-free solder and on reducing the flip chip pitch down to 40 μm, in line with future enhanced capabilities in wirebonding technolo
机译:作为欧洲项目“Cirrus”的一部分,已经开发出超薄IC包。包装,呈“腔腔”超薄EGA的形状,具有168 iOS和测量9 * 9毫米。插入器是50μm厚的聚酰亚胺弯曲,具有带Cu / Ni / Au堆叠的扇出构建。对于本设计,使用100μm的粘合剂间距使用5×5mm的IC。该封装具有标准化板界面,球间距为0.5毫米。通过使用具有低倒装芯片凸块(20微米)的稀入模具(150μm)与各向异性导电粘合剂组合来实现最终的高度降低。母板上焊料回流后的所得高度限制在300μm。在论文中,将对第二级互连的第一级和共面值的流程调查进行处理。进一步的工作旨在使用无铅焊料实现与箔片的芯片连接,并将倒装芯片间距降低至40μm,这符合Wiebonding Technolo中的未来增强功能

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