The impact of as dopants in ldd inplantation on junction leakage of dram cells

摘要

This paper reports the effects of arsenic dopants in lightly doped drain (LDD) implantation of a DRAM chip. The experimental results show that the node junction leakage decreases by more than 10percent and the retention time increases by more than 100 msec without arsenic. One possible cause is that the implantation damage by the heavier arsenic ions is more severe. However, source/drain characteristics are adversely affected by the removal of arsenic dopants. Among them, parasitic resistance (R_(sd)) increases, and consequently NMOS saturation current and transistor switching speed are reduced. Source/drain junction becomes deeper and less abrupt. Hence, short channel effect is more evident. Drain Induced Barrier Lowing (DIBL), threshold voltage roll-off and higher standby current are more prominent without arsenic during technology scaling. In short, LDD implantation without arsenic shows better junction leakage and retntion time results. Nevertheless, the trade-off from device performance should be taken into account.