Mathematical Model for the Output Signal's Energy of an Ideal DAC in the Presence of Clock Jitter

摘要

A mathematical model for the output signal's energy of a multidimensional ideal DAC is presented considering sampling clock jitter. More specifically, a new model is formulated to prove one-sided energy inequality for the output signal, for which the base time is affected by the jitter. Moreover, a family of annihilate operators is defined and applied to the ideal (one-dimensional) DAC model to estimate the output signal energy.