Modeling Random Clock Jitter Effect of High-Speed Current-Steering NRZ and RZ DAC

摘要

In this paper, signal-to-noise ratio (SNR) degradation from random clock jitter in a current-steering digital-to-analog converter (CS-DAC) is analyzed based on a timing-to-amplitude error conversion method. A closed-form equation is derived to predict SNR for white noise clock jitter (WN-J) and low-pass filtered clock jitter (LPF-J) in non-return-to-zero (NRZ) and return-to-zero (RZ) DAC. Especially for the clock source with LPF-J, our equation predicts that the return-to-zero (RZ) DAC SNR is better than what the conventional analysis foresees due to the high-pass filter function derived in our analysis. Our analysis completely captures both WN-J and LPF-J in NRZ and RZ DAC, and is verified in both MATLAB simulation and measurement with the difference of less than 2 dB.