A Flexible Manufacturing Method for Wafer Level Packages

摘要

There are some common and well known trends in Wafer Level Packaging driven by the surge in advanced mobile products. Silicon nodes are shrinking from 32nm to 28nm to 20nm and below and packaging materials and processes need to adapt to these node without causing damage to the new more fragile structures. Product form factors are shrinking with the requirement for higher I/O count and greater complexity in ever smaller package sizes. There is increase integration of active and passive components into single packages in novel PoP and SiP configurations. At the same time there is extreme pressure to reduce cost. Effective cost reduction strategies are critical for current and future technologies. Typical annual cost reductions of ～5% are expected for a mature technology based on manufacturing efficiency, scaling, and materials cost reduction, but it is difficult to achieve additional and dramatic cost reductions on a mature WLP technology.