Selective Etches for Gate-All-Around (GAA) Device Integration: Opportunities and Challenges

摘要

This paper addresses the opportunities and challenges of wet and dry selective etches in the integration of gate-all-around (GAA) field-effect transistor (FET), which is emerging as a promising solution to replace FinFET for the advanced logic devices. For the GAA device fabrication, a quintessential challenge is a controlled isotropic etching of dielectrics, semiconductors, and metals with high selectivity to the exposed materials. In this paper, the significance of the unit process modules in the GAA device integration: shallow trench isolation (STI), inner spacer formation, replacement metal gate (RMG) and self-aligned interconnect in the middle-of-line (MOL) and the back-end-of-line (BEOL), will be discussed.