The static and dynamic analysis of the thermal resistance (R_(TH)) in 65nm SOI DriftMOS power devices is presented in this work. Experiment and numerical simulation are both used to compare DriftMOS devices integrated in 65nm and 130nm SOI technologies. Important R_(TH) drop (between 40% and 60%) is found by experiment at 65nm technology, basically due to the thinner buried oxide (BOX) layer. However, numerical simulation reveals a lower R_(TH) reduction in the hottest point of the SOI active layer, shifted down about 15%. Furthermore, the R_(TH) dependence with device geometrical parameters is investigated and the different layer contributions to the global thermal resistance are identified.
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机译：在这项工作中介绍了65nm SOI Driftmos电力设备中的热阻（R_（TH））的静态和动态分析。实验和数值模拟两者都用于比较漂移在65nm和130nm的SOI技术中集成的Driftmos器件。通过在65nm技术的实验中发现重要的R_（Th）液滴（40％和60％），基本上是由于较薄的掩埋氧化物（箱）层。然而，数值模拟显示了SOI有源层最热点的较低的R_（th）降低，移位约15％。此外，研究了与器件几何参数的R_（Th）依赖性，并且识别出对全局热阻的不同层贡献。
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